The present invention relates to a semiconductor device that ensures a reduction in a process-induced damage (hereinafter abbreviated as xe2x80x9cPIDxe2x80x9d) in a multilevel interconnection process.
According to the related art technology in the field, a semiconductor device is designed by the following method.
A logic circuit which satisfies a given operation is laid out with a device isolation pattern, an impurity doping pattern, a gate electrode pattern, a contact hole pattern and a first metal interconnection pattern. The first metal interconnection pattern is so designed that its antenna ratio becomes equal to or smaller than an allowable antenna ratio.
Then, a first via pattern for connecting the first metal interconnections to the second metal interconnections is laid out. The first via pattern is so designed that its antenna ratio becomes equal to or smaller than the allowable antenna ratio.
A second metal interconnection pattern is then laid out. The second metal interconnection pattern is so designed that its antenna ratio becomes equal to or smaller than the allowable antenna ratio.
The semiconductor device is designed by repeating the second stage and third stage until a predetermined number of interconnection levels is reached.
The disclosed method of the related art could not however completely prevent a PID-oriented variation in transistor characteristic or deterioration of the characteristic. The problem is reported in detail in xe2x80x9cImpact of pattern density on plasma damage of CMOS LSIs, K. MIYAMOTO et al., Technical digest of International Electron Devices Meeting, pp. 739-742, 1996xe2x80x9d. The problem will be elaborated hereunder according to the reference document.
The numbers of defective transistors generated on SRAM test chips were examined with respect to Random Logic A, Random Logic B and RAM and came out in the order of Random Logic A greater than Random Logic B greater than RAM. An antenna ratio, a typical PID index, was also studied for each of the three functional elements. The antenna ratios came out in the order of Random Logic A greater than RAM greater than Random Logic B. Apparently, the tendency of the antenna ratio did not match with the tendency of the number of defective transistors. It is to be noted that the antenna ratio is calculated in terms of interconnections and vias and is equal to the interconnection side area divided by the transistor area and the via bottom area divided by the transistor area. The pattern ratios of the functional elements were in the order of RAM greater than Random Logic A greater than Random Logic B. It was concluded from the above that the PID was a function of the antenna ratio and the pattern ratio and the larger the antenna ratio was and the smaller the pattern ratio was, the easier the generation of the PID became.
The influence of the pattern ratio on the PID was also reported in xe2x80x9cQuantifying Via Charging Currents, Wes Lukaszek et al., Proceedings of 2nd International Symposium on Plasma Process-Induced Damage, pp. 123-126, 1997xe2x80x9d. The following is the specific discussion on the influence given in the document.
For vias of size 1.5 xcexcm and different density levels 1/1600 (/xcexcm2) for v1, 1/400 (/xcexcm2) for v4, 1/100 (/xcexcm2) for v16, and 1/25 (/xcexcm2) for v64 the voltage dependency of the current density was examined by a charge-flux sensor. It was confirmed that the current density increased only for the density level of v1 among the four density levels.
As apparent from the two documents, it is necessary to pay attention to both the antenna ratio and the pattern density in order to suppress the PID. Accordingly, it is an object of the invention to provide a method of fabricating a semiconductor device, which can suppress the PID in consideration of the influences of the antenna ratio and the pattern density.
In a method of fabricating a semiconductor device of the present invention, first metal interconnection patterns (M1a), first via patterns (V1a) and second metal interconnection patterns (M2a) are positioned in such a way that each of antenna ratios of the first metal patterns, the first via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio. Next, a width of each of the first metal patterns (M1a) is broadened by a minimum line width of the first metal patterns to form broadened first metal patterns (M1b). The broadened first metal patterns (M1b) are connected at a first area where a distance between the broadened first metal patterns is smaller than a minimum size of the first via patterns (V1a) o form modified first metal patterns (M1c). Then, a second area is extracted where the first metal patterns (M1c) and the second metal patterns (M2a) do not exist. Additional first via patterns are placed in the second area. Each of the additional first via patterns (V1b) has a minimum size with a minimum pitch in the second area. Finally, the additional first via pattern which do not meet a minimum allowable distance between the first metal patterns (M1c) and the first via patterns is deleted to form the finally additional first via patterns (V1c). After all of the above data processes are conducted, the first metal patterns are fixed at M1a and the first via patterns are fixed at V1a+V1c.